Optimization & Reliability Studies of Power Electronic Modules (GR-15-01)

Principal Investigator: Dr. Simon Ang

With the power density in power electronic industry increasing rapidly, power electronic modules offer attractive solutions to improve performance. It is necessary to investigate various power electronic module issues to achieve high current and high voltage specifications required by many typical grid-tied power electronic applications. In the first phase of this project, substantial efforts have been performed on improving the breakdown voltage capability and module architecture of these power electronic modules. Due to the high defect density in the starting silicon carbide substrates, large area and hence, large current rated SiC power semiconductor devices are not currently very practical. As such, it is necessary to parallel many of these SiC power semiconductor devices together in one switching position to increase its current handling capability. Paralleling of SiC power semiconductor devices creates problems for dynamic switching of these individual SiC power devices due to their different equivalent parasitic circuit elements. Besides dynamic switching, these switching positions that comprised of many paralleled SiC devices are prone to emit electromagnetic interference (EMI) due to these imbalance parasitic circuit elements and large current path areas. Moreover, reliability of these paralleled SiC devices must be investigated in high current switching operation for reliable deployment of these SiC power electronic modules. As such, power cycling and temperature cycling of these power modules will be conducted.
From parasitic and circuit simulation techniques, mitigation of parasitic inductances as well as balancing of parasitic inductances among these paralleled SiC devices are important to improving the dynamic turn-on of these individual devices. The traditional co-planar design approach has limitations in terms of having a large substrate area due to the required current paths, placement of the I/O terminals, Kelvin connections for gate-source circuits, and the number of bond wires required. All these not only contribute to a large parasitic inductance but also create the unbalance dynamic switching on in these individual devices. Moreover, the EMI emission of a power electronic module partly depends on the area of the current conduction path and layout topology with a smaller area contributing to a lower EMI emission. Thus, a three dimensional (3-D) multilayer approach is more suitable both in terms of reducing parasitic inductance and EMI emission of power electronic modules. This project will cover investigation of the parasitic inductance minimization techniques to optimize dynamic switching of high current SiC power electronic modules. EMI compatibility and reliability assessment of different physical layout techniques in terms of electrical and thermal performances will also be investigated.


Posted on

July 1, 2015

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