Development of GaN based Compact Scalable Multilevel Inverter Building Block (23-07)

Principal Investigator: Dr. Xiaoqing Song Power inverters are widely used in grid tied converters, energy storage, PV system, datacenters and motor drives. The state-of-the-art inverter topology in most applications is standard 2-level voltage source converter (2L-VSC) topology realized by SiC MOSFETs or Silicon (Si) IGBTs depending on the manufacturer. Despite its ruggedness and simplicity in PWM modulation, the 2L-VSC produces an output voltage switching between V+ DC and V- DC, which introduces higher THD and EMIs. A high DC bus voltage (700V~900V) will even worsen the THD and EMI problems due to higher dv/dt. The multilevel inverter topology has less THD and lower switching dv/dt compared to the standard 2L VSC, resulting in lower current ripple, smaller output filters and EMI noises. The project will develop and demonstrate a GaN based high power density multilevel (40kW/L with liquid cooling or 25kW/L with forced air cooled) inverter. A 25kVA multilevel inverter building block with scalability will be demonstrated and multiple inverter building blocks can be connected in parallel to achieve high power ratings (100kVA and above). The very high switching dv/dt (up to 40~50kV/μs) of GaN devices, on one hand, is beneficial in switching losses reduction and high converter efficiency. On the other hand, the fast-switching speed also causes excessive voltage overshoot during turn-off transient, lead to elevated EMI emissions and pose additional challenges in the power loop and gate loop design. To address that, advanced PCB technologies with optimized layout and mechanical structure is designed to ensure the fast-switching speed of the GaN FETs. Upon the completion of the project, we expect to deliver a high-efficiency, high-density GaN based 25kVA, 3-level inverter building block, and experimentally evaluate and demonstrate the developed inverter at 700V~900V DC bus voltage. Specially, we will explore the benefits of high switching frequency of the GaN devices on the inverter output filter (LC filter or LCL filter) design. How the high switching frequency can benefit the size reduction and cost reduction of the filter will be evaluated quantitatively.